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/* here see um_s3c4510b.pdf 5-4 */
/*
NON-CACHEABLE AREA CONTROL BIT
Although the cache affects the entire system memory, it is sometimes necessary to define non-cacheable areas
when the consistency of data stored in memory and the cache must be ensured. To support this, the S3C4510B
provides a non-cacheable area control bit in the address field, ADDR[26].
If ADDR[26] in the ROM/SRAM, flash memory, DRAM, or external I/O bank's access address is "0", then the
accessed data is cacheable. If the ADDR[26] value is "1", the accessed data is non-cacheable.
*/
/*
Special thanks to gongxufei <[email protected]> for this great contribution
*/
// for USB DATA and COMMAND, set addr[26] = 1 so the accessed data is non-cacheable
#define D12_DATA 0x07fd0000 //D12 use nECS0 as the chip selection
#define D12_COMMAND 0x07fd0001
1.代码注释中提到如果ADDR[26] = 1,那么访问数据时就是非缓冲方式,请问ADDR[26]是什么?
2.D12_DATA 和D12_COMMAND 的地址是怎么确定的?(没有看到相关寄存器的设置) |
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