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楼主 |
发表于 2009-8-3 21:47:42
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原因
在skyeye做如下修改:
skyeye_mach_s3c241x.c:
static void
s3c2410x_update_int (ARMul_State * state)
{
ARMword requests;
s3c2410x_update_subsrcint ();
s3c2410x_update_extint ();
requests = io.srcpnd & (~io.intmsk & INT_MASK_INIT);
state->NfiqSig = (requests & io.intmod) ? LOW : HIGH;
state->NirqSig = (requests & ~io.intmod) ? LOW : HIGH;
if (!state->NirqSig)
fprintf(stderr, "s3c2410x_update_int 0x%x 0x%x %d\n", io.subsrcpnd, io.srcpnd, state->NirqSig);
}
static void
s3c2410x_uart_read (u32 offset, u32 * data, int index)
{
switch (offset) {
case ULCON:
*data = io.uart[index].ulcon;
break;
case UCON:
*data = io.uart[index].ucon;
break;
case UFCON:
*data = io.uart[index].ufcon;
break;
case UMCON:
*data = io.uart[index].umcon;
break;
case UTRSTAT:
*data = io.uart[index].utrstat;
break;
case UERSTAT:
*data = io.uart[index].uerstat;
break;
case UFSTAT:
*data = io.uart[index].ufstat;
break;
case UMSTAT:
*data = io.uart[index].umstat;
break;
case URXH:
/* receive char
* */
*data = io.uart[index].urxh;
io.uart[index].utrstat &= (~0x1); /* clear strstat register bit[0] */
io.uart[index].ufstat &= ~(0x1); /* 2007-02-09 by Anthony Lee : for 0 bytes */
break;
case UBRDIV:
*data = io.uart[index].ubrdiv;
break;
default:
break;
}
fprintf(stderr, "%s(UART%d: 0x%x, 0x%x)\n", __FUNCTION__, index, offset, *data);
}
static void
s3c2410x_uart_write (ARMul_State * state, u32 offset, u32 data, int index)
{
fprintf(stderr, "%s(UART%d: 0x%x, 0x%x)\n", __FUNCTION__, index, offset, data);
switch (offset) {
case ULCON:
io.uart[index].ulcon = data;
break;
case UCON:
io.uart[index].ucon = data;
break;
case UFCON:
io.uart[index].ufcon = data;
break;
case UMCON:
io.uart[index].umcon = data;
break;
case UTRSTAT:
io.uart[index].utrstat = data;
break;
case UERSTAT:
io.uart[index].uerstat = data;
break;
case UFSTAT:
io.uart[index].ufstat = data;
break;
case UMSTAT:
io.uart[index].umstat = data;
break;
case UTXH:
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(index, &c, 1, NULL);
io.uart[index].utrstat |= 0x6; //set strstat register bit[0]
if ((io.uart[index].ucon & 0xc) == 0x4) {
s3c2410x_set_subsrcint (UART_INT_TXD << (index * 3));
s3c2410x_update_int (state);
}
}
break;
case UBRDIV:
io.uart[index].ubrdiv = data;
break;
default:
break;
}
}
static void
s3c2410x_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
if ((addr >= UART_CTL_BASE0)
&& (addr < UART_CTL_BASE0 + UART_CTL_SIZE)) {
s3c2410x_uart_write (state, (addr - UART_CTL_BASE0) % 0x4000,
data, (addr - UART_CTL_BASE0) / 0x4000);
return;
}
if ((addr >= PWM_CTL_BASE) && (addr < (PWM_CTL_BASE + PWM_CTL_SIZE))) {
s3c2410x_timer_write (state, addr - PWM_CTL_BASE, data);
return;
}
/*
* 2007-02-09 by Anthony Lee
* changed 0xC0 to 0xA4 for running linux-2.6.20,
* because GSTATUS1 is 0xB0, the "0xC0" make it like S3C2400
*/
if((addr >= GPIO_CTL_BASE) && (addr < (GPIO_CTL_BASE + 0xA4))){
int offset = addr - GPIO_CTL_BASE;
io.gpio_ctl[offset] = data;
return;
}
switch (addr) {
case SRCPND:
fprintf(stderr, "write srcpnd step 1: 0x%x 0x%x\n", io.subsrcpnd, io.srcpnd);
io.srcpnd &= (~data & INT_MASK_INIT);
fprintf(stderr, "write srcpnd step 2: 0x%x 0x%x\n", io.subsrcpnd, io.srcpnd);
//2006-04-04 chy, for eCos on s3c2410. SRCPND will change the INTPND, INTOFFSET, so when write SRCPND, the interrupt should be update
s3c2410x_update_int (state);
fprintf(stderr, "write srcpnd step 3: 0x%x 0x%x\n", io.subsrcpnd, io.srcpnd);
break;
case INTMOD:
io.intmod = data;
break;
case INTMSK:
io.intmsk = data;
s3c2410x_update_int (state);
break;
case PRIORITY:
io.priority = data;
break;
case INTPND:
io.intpnd &= (~data & INT_MASK_INIT);
io.intoffset = 0;
//printf ("io.intoffset:%x, io.intpnd:%x (0x%08x) = 0x%08x, pc:%x\n", io.intoffset, io.intpnd, addr, data, state->pc);
break;
/*read only */
//case INTOFFSET:
// break;
case SUBSRCPND:
fprintf(stderr, "write sub_srcpnd step 1: 0x%x 0x%x\n", io.subsrcpnd, io.srcpnd);
io.subsrcpnd &= (~data & INT_SUBMSK_INIT);
fprintf(stderr, "write sub_srcpnd step 2: 0x%x 0x%x\n", io.subsrcpnd, io.srcpnd);
break;
case INTSUBMSK:
io.intsubmsk = data;
break;
/* ext interrupt */
case EINTMASK:
io.eintmask = data;
break;
case EINTPEND:
io.eintpend &= (~data & 0x00FFFFF0);
break;
case CLKCON:
io.clkpower.clkcon = data;
break;
case CLKSLOW:
io.clkpower.clkslow = data;
break;
case CLKDIVN:
io.clkpower.clkdivn = data;
break;
case BWSCON:
io.memctl.bwscon = data;
break;
case MPLLCON:
io.clkpower.mpllcon = data;
break;
case BANKCON0:
io.memctl.bankcon[0] = data;
break;
case BANKCON1:
io.memctl.bankcon[1] = data;
break;
case BANKCON2:
io.memctl.bankcon[2] = data;
break;
case BANKCON3:
io.memctl.bankcon[3] = data;
break;
case BANKCON4:
io.memctl.bankcon[4] = data;
break;
case BANKCON5:
io.memctl.bankcon[5] = data;
break;
case BANKCON6:
io.memctl.bankcon[6] = data;
break;
case BANKCON7:
io.memctl.bankcon[7] = data;
break;
case REFRESH:
io.memctl.refresh = data;
break;
case BANKSIZE:
io.memctl.banksize = data;
break;
case MRSRB6:
io.memctl.mrsrb6 = data;
break;
case MRSRB7:
io.memctl.mrsrb7 = data;
break;
case WDCON:
io.wd_timer.wtcon = data;
break;
case WDDAT:
io.wd_timer.wtdat = data;
break;
case WDCNT:
io.wd_timer.wtcnt = data;
break;
default:
SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data);
break;
}
}
[ 本帖最后由 wt133664 于 2009-8-3 21:51 编辑 ] |
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